The present invention relates to a phase-locked loop (PLL) circuit used for a semiconductor integrated circuit.
A PLL circuit includes: a phase/frequency detector for detecting phase/frequency difference between two input signals; a charging pump circuit for converting the phase/frequency difference, detected by the phase/frequency detector, into a current value; a low-pass filter for converting the sum of current, supplied from the charging pump circuit, into a voltage value; a voltage-controlled oscillator having an oscillation frequency variable with a voltage value thereof; and (if necessary) a divider circuit for dividing the frequency of the output signal of the voltage-controlled oscillator.
Hereinafter, a conventional PLL circuit will be described with reference to FIG. 8.
FIG. 8 is a block diagram of a conventional PLL circuit. As shown in FIG. 8, the PLL circuit includes: a phase/frequency detector (PFD) 110; a charging pump circuit (CP) 120; a low-pass filter (LPF) 31; a voltage-controlled oscillator (VCO) 32; a divider (1/N) 33 for dividing the frequency of an input signal by N; an input pin IN; and an output pin OUT. REFCLK denotes a reference signal externally input through the input pin IN. And DEVCLK denotes a signal produced by the PLL circuit.
The conventional PLL circuit shown in FIG. 8 operates in the following manner. The phase/frequency detector 110 compares the phase/frequency of the reference signal REFCLK to that of the produced signal DEVCLK, and provides the phase/frequency difference to the charging pump circuit 120. The charging pump circuit 120 converts the phase/frequency difference between the reference signal REFCLK and the produced signal DEVCLK into a current value. The sum of these current values is converted by the LPF 31 into a voltage value. The transfer function from the phase/frequency detector 110 to the LPF 31 can be represented as Kp [V/rad].
The VCO 32 oscillates at a predetermined frequency in accordance with the value of an input voltage. The transfer function of the VCO 32 can be represented as Kv [rad/sV]. The loop ranging from the phase/frequency detector 110 to the VCO 32 can synchronize the frequency of the reference signal REFCLK with that of the produced signal DEVCLK. Phase locking of a PLL circuit refers to this synchronization between the frequency of the reference signal REFCLK and that of the produced signal DEVCLK.
In FIG. 8, the oscillated output signal of the VCO 32 is not only output through the output pin OUT, but also input to the phase/frequency detector 110 as the produced signal DEVCLK after the frequency thereof has been divided by the divider 33 by N. In such a configuration, the PLL circuit may output a signal, the frequency of which is N times as high as that of the reference signal REFCLK.
However, in the conventional PLL circuit, the transfer function Kp from the phase/frequency detector 110 to the LPF 31 is constant irrespective of the magnitude of the phase/frequency difference between the reference signal REFCLK and the produced signal DEVCLK. Thus, for example, if the phase/frequency difference between the reference signal REFCLK and the produced signal DEVCLK is large in an initial state, then it takes a rather long time for the PLL circuit to accomplish phase locking.
In order to get the PLL circuit to accomplish phase locking in a shorter period of time, it is effective to set the transfer function Kp from the phase/frequency detector 110 to the LPF 31 at a larger value. If the transfer function Kp is simply increased, then the phase/frequency difference is much smaller until just before the PLL circuit accomplishes phase locking. However, since the value of a dumping factor .xi. becomes larger, various problems possibly happen. For example, large jitter may be generated or locking may be incomplete.